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Power Loss Protection (PLP) for SSD and MCU

Lecture



Power Loss Protection (PLP) for SSDs is not a new concept, but the ways and methods of protecting SSDs during and after a power failure have significantly improved in modern SSD models. The purpose of power loss protection is to accomplish two main tasks:

  • Safely transfer data in transit (or data remaining in the DRAM or SRAM cache buffers of the drive) to permanent non-volatile flash memory, and
  • Preserve the integrity of the SSD's mapping table so that the SSD is recognized and usable after a system reboot.

Note: the SSD mapping table, or Flash Translation Layer (FTL), is responsible for the logical distribution of physical data on the SSD.

Under conditions of a normal system shutdown, the SSD receives a command (Standby Immediate Command) from the host's ATA driver, warning the SSD of the system shutdown so that the SSD can prepare for a power interruption. During a normal system shutdown, the SSD has enough time to transfer data from the cache buffers and update the mapping tables.

High-quality SSDs use a hardware system with power capacitors built into the SSD and/or power loss protection (PLP) in firmware, allowing critical metadata to be written to flash memory to ensure successful SSD recovery upon power-up. Currently, Kingston products use tantalum polymer capacitors to implement the PLP function.

Early SSD models were not as well prepared for sudden power loss as modern ones. Typically, an SSD that experienced a sudden power loss would not respond on the next power cycle. In many such cases, power failures led to SSD failure and data loss.

PLP Implementation Options

Hardware PLP – hardware PLP is primarily designed to reduce data loss by maintaining SSD power, thanks to built-in power capacitors (Power Caps), for a time sufficient to write data remaining in the SSD's cache buffer to flash memory and update the mapping tables. The general scheme of a typical hardware PLP case in an SSD looks approximately as follows:

The SSD controller detects a sudden power loss

  1. Built-in power capacitors maintain power for the SSD
  2. The controller issues an internal command to transfer data from the cache buffer
  3. The controller updates the mapping tables, preparing for power-off
  4. The drive safely shuts down

Firmware PLP – software PLP protection is also designed to reduce the likelihood of data loss thanks to the firmware's ability to restore the mapping table on the next power-up after a failure. The general scheme of a typical firmware PLP protection case looks approximately as follows:

  1. The SSD mapping table is stored in flash memory and updated in DRAM
  2. When new data is written to the SSD, the firmware updates the mapping table
  3. Newly written data is always written with tags (or spare bytes) including the LBA, ECC, and other data structure information
  4. A power failure occurs
  5. The spare bytes containing data structure information, together with the original mapping table, allow the SSD firmware to restore the SSD mapping table at the next power-up

Firmware PLP protection is a highly effective way to prevent data loss in enterprise storage systems. For example, SSDs configured in RAID arrays need to be able to recover and return to a healthy state after a power failure in order to maintain the integrity of the RAID array. One or more failed drives in the array will result in the array shutting down with a high probability of data loss.

In another enterprise system scenario, SSD drives can form a large storage pool in which physical SSDs are divided into multiple LUNs and shared among multiple hosts. In this example, a critical characteristic is high availability, and firmware-based PFAIL protection ensures successful recovery of the SSD serving the LUNs and hosts.

By putting client SSDs into servers, owners create, with their own hands, the conditions for their possible corruption or even loss. Unlike server-grade drives, consumer drives have no power loss protection (PLP).

The purpose of DRAM

Although SSDs are built on non-volatile NAND memory, they contain a volatile buffer (DRAM cache). Upon receiving a write request from the OS, the SSD controller places a portion of the data into this buffer – to improve performance and optimize writes. Until the data reaches the NAND cells, it is at risk – a loss of power to the dynamic memory results in the loss of its contents, and what the OS considers a completed fact – a write to NAND – does not actually happen at all. It would be fine if only a small portion of data were lost. In the absence of end-to-end data integrity checking (for example, on the part of the file system), errors accumulate and lead to data corruption (GIGO – Garbage In, Garbage Out).

Power Loss Protection (PLP) for SSD and MCU

Power Loss Protection (PLP) for SSD and MCU

The second purpose of SSD DRAM – caching metadata, address tables in the FTL (Flash Translation Layer). Each new host write request updates the FTL. In addition, addresses change as a result of background controller activity such as garbage collection and wear leveling. For these operations the controller uses DRAM, which has bit-level addressing, lower latency compared to NAND cells, and virtually unlimited rewrite endurance.

Power Loss Protection (PLP) for SSD and MCU

Fig. 1. Upon a normal system shutdown, data is flushed to NAND flash memory, and the SSD signals the host that the drive is ready for power-off.

How an Unsafe Shutdown Affects an SSD

When the host wants to write data to the SSD, the data is first stored in a temporary buffer (volatile memory), if the SSD has a DRAM cache, before it is flushed to non-volatile flash memory for safe storage; otherwise the data is stored directly in NAND flash memory (non-volatile memory), where it is stored safely even in the event of a power loss.

During a normal system shutdown, the host first warns the SSD that the system is shutting down. The SSD then prepares for power-off, flushes data from volatile storage to non-volatile flash memory, and then signals the host that the drive is ready to be powered off.

This process solves two important tasks: first, it ensures that data is safely stored before power-off; and second, the mapping tables are updated. The mapping tables track logical block addresses in relation to the physical pages of flash memory, indicating where the data is stored on the flash drive.

An unsafe shutdown occurs when power is cut before the shutdown notification is completed. This prevents data from being moved out of the temporary buffers ("flushed") into the non-volatile NAND, which leads to data corruption or loss, or renders the storage device unusable. Examples of unsafe shutdowns include unexpected power outages, accidental removal of the solid-state drive from a computer, disconnecting the storage device while powered on, or loss of battery charge.

Solid-state drives are especially vulnerable to power loss events. Unlike hard disk drives, solid-state drives have no mechanical parts, so every component is electronic. Internal data management on a solid-state drive involves many operations performed in the background, and any power failure can mean an excessive interruption of those operations, which can affect the drive's performance.

Unstable Power

You protected yourself from external power surges with a UPS, but the server's power supply died… Or the I/O controller. Or the motherboard. A client machine going down will not lead to serious consequences. But an enterprise server is a tool of collective work, and data integrity and availability have the highest priority. Higher risks, higher responsibility.

Commercial-grade SSDs have power protection – capacitors: aluminum, tantalum, ceramic, etc. Their residual charge provides a temporary window sufficient to flush data from the buffer into NAND and update the addressing tables.

Power Loss Protection (PLP) for SSD and MCU

PLP pursues two goals:

  • Safely transferring the data itself from the SSD's volatile DRAM memory into permanent NAND;
  • Preserving a valid table for translating physical addresses to logical ones – for correct continuation of operation after a restart.

Due to the high cost of capacitors and the price sensitivity of the client SSD market, hardware PLP protection is not installed on them. At best, a software half-measure is applied: metadata logging at the FTL and file system level. If this is implemented in SSD firmware, when new data is written, tags (spare bytes) are written to a separate log file, including the logical block addresses (LBA), error correction codes (ECC), and other structural information. After a system restart and log verification, the original address tables are restored. (Data in the buffer at the time of the incident is lost in any case.)

In the world of PCs, data loss is not as critical – due to its comparatively low value. In addition, many modern file systems already use journaling. The sources of risk are not new either – a cache buffer (DRAM cache) is present in any HDD, and it is usually not disabled. Enterprise and data center servers and storage systems are a completely different matter. Even a small probability of loss must be taken into account – data and reputation are worth more.

What if you disable the cache?

The cache buffer speeds up the processing of host I/O requests and is used to prepare clean pages for writing – reducing wear on the SSD cells.

Enable the cache on an SSD without PLP – and you risk losing data. Disable it – and you lose performance and shorten the SSD's lifespan. Without a buffer in dynamic memory, an SSD's operation will be sluggish, and its life short. In Write Through mode, consumer drives do not outperform HDDs:

Power Loss Protection (PLP) for SSD and MCU

«Oh, how inconvenient this turned out to be».

How to determine whether an SSD has PLP?

Read the documentation. SSD manufacturers state directly what type of application their products are intended for. Tempted by a low price and saving the user's money (did he ask you to?), you put him at risk without his consent

Microcontrollers: providing next-generation power loss protection

Power loss protection (PLP) mechanisms are available on most solid-state drives, especially those designed for high-performance applications. Such industrial-grade storage devices are typically widely used in harsh conditions, operate around the clock, and require uncompromising device integrity.

Typical PLP solutions include the use of batteries and supercapacitors, which provide a power hold-up delay, allowing controller and flash functions to be completed in the event of a power failure.

ATP Electronics, one of the first companies to develop and release smaller form-factor solid-state drives, such as the M.2 2242 with a built-in PLP array, is taking things a step further by using a microcontroller (MCU) that provides unprecedented protection for the next-generation serial port. ATA and NVMe solid-state drives for the industry's best PLP protection.

How MCUs improve the PLP mechanism

Integrated into the ATP PowerProtector 4, the brand-new PLP array design uses a new power management IC (PMIC) and a new microcontroller with firmware that allow the PLP array to work intelligently across various temperatures, power failures, and power states.

Power Loss Protection (PLP) for SSD and MCU

Fig. 1. New PLP array from ATP with PMIC and a microcontroller programmable via firmware.

  • The microcontroller intelligently monitors power failure conditions and checks the state of the capacitors via the I 2 C interface.
  • Polymer tantalum capacitors provide sufficient backup power to flush the data cache in the event of an unexpected power loss.
  • The MCU can continuously detect power failure conditions; for example, for a 2.5-inch SSD, if the input voltage drops below 4.0 V for several consecutive milliseconds (debouncing), the MCU will notify the controller to begin flushing the cache, and at the same time the capacitors will be activated to provide continuous power to complete the cache flush.

Power Loss Protection (PLP) for SSD and MCU

Fig. 2. MCU-based design implemented in the latest ATP NVMe SSD.

Features and Benefits

  • Protection against input overvoltage. Input voltage refers to the voltage supplied to the circuit. SSDs typically have a specific range within which the input voltage is allowed - for example, for ATP 2.5-inch SSDs the upper limit is 16 V, while for other SSDs it is 7 V. When the input voltage is higher than specified, it can cause irreversible damage to the components.

The next-generation ATP SSDs have a switch between the external input voltage and the internal SSD circuitry. This switch is controlled by the MCU. Since the input voltage is monitored by the microcontroller in real time, it protects the SSD by sending a signal to the protective switch to disconnect the input voltage as soon as it is detected to exceed the specified maximum tolerance.

  • Suppression of inrush current at power-on. Inrush current at power-on is a large current drawn by the system at the moment it is switched on. This initial current, also known as inrush surge current or input surge current, is required to charge the capacitors, inductors, and transformers. Excessively high inrush current can damage the circuits and components. The MCU-based design available on the latest ATP SATA and NVMe SSDs ensures that the inrush current does not exceed the set threshold values, by enabling a soft-start mechanism that minimizes the impact of inrush current on the SSD.

  • Elimination of input power noise. Input power noise refers to a situation where the power source is unstable, causing unwanted periodic ripples and surges.

The MCU helps eliminate noise glitches using an evaluation mechanism that determines when power drops below a certain value, thereby correctly identifying power loss versus simple power instability. Without the MCU, power instability could be mistakenly interpreted as a power failure and thus falsely trigger a cache flush, potentially leading to the SSD "hanging" or freezing.

  • Fast power-on and power-off. Power on/off control refers to the mechanism that regulates the time between power-off and the next power-on. The MCU design can provide faster and more efficient power on/off control. The following table shows the advantages of SSDs with MCU-based control compared to SSDs that lack it:

Table 1. SSD power on/off with / without MCU

SSD without MCU

SSD with MCU

PLP capacitors need to be discharged / reset before power-on

Immediate power-on is initiated regardless of the residual voltage on the PLP capacitors

If the power-off state is very short:

  • PLP may not discharge fully
  • Controller reset may fail
  • The SSD may not be recognized and will fail to reboot

If the power-off state is very short:

  • No need for full PLP discharge
  • The MCU resets the controller
  • The SSD can be recognized and will reboot correctly

Thanks to MCU-based PLP, fast power on/off can be guaranteed without the potential risk of drives going undetected due to improper controller reset.

  • Overvoltage protection for PLP capacitors

Polymer tantalum capacitors are essential elements of ATP's PLP technology. By providing backup power, they ensure that data from the DRAM cache will be flushed to NAND flash for safe storage, and the last write command will be completed when a power loss event occurs.

Overcharging can damage the capacitors and thereby compromise their protective function. The MCU monitors the capacitor voltage in real time and disables charging as soon as it detects that the voltage is too high. This ensures that the PLP capacity is sufficient to complete the cache flush during a power failure. It also prevents premature aging of the PLP capacitors.

Summary and Conclusion

The ATP PowerProtector 4 combines an MCU-based design to provide advanced power management and PLP capabilities for next-generation ATP SATA and NVMe SSDs. By combining hardware and firmware solutions, the MCU-based design protects the data as well as the storage device, providing a higher level of integrity and reliability. Depending on customer request, advanced features can be customized, allowing PLP capabilities to be tailored to the unique requirements, needs of a specific application, or use cases.

The following table lists the benefits of each feature.

Table 2. Summary table showing how each MCU feature and benefit provides advanced PLP capabilities for the latest ATP SSDs and modules.

Improved drive protection

  • Suppression of inrush current at power-on
  • Overvoltage protection

Better data integrity

  • Input power, noise, glitch / overcharge protection
  • PLP capacitors protection against undercharge / overcharge

Fast power on / off

  • Reduces the time required from power-off to powering the SSD back on.

Precise control of power on / off sequences

  • Prevents potential issues when powering the SSD on / off

Customization options

  • PLP can be tailored according to customer requirements or the requirements of a specific application.

Next-generation ATP SSDs with the new MCU-based design include mSATA, 2.5-inch SSDs, M.2 2242/2280 modules, and NVMe. Available with I-Temp and C-Temp support, the SSDs also feature RAID mechanism support and end-to-end data path protection. ATP's solutions, designed exclusively for industrial use, undergo rigorous testing and validation to meet the high reliability, performance, and durability requirements of mission-critical applications, ensuring the best total cost of ownership (TCO). For more information about ATP's MCU-based industrial flash drives, visit the ATP website or contact an ATP representative .

See also

  • Hard disk drive
  • SSD

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