Out-of-Order Execution

Lecture



Out-of-order execution (English: out-of-order execution) of machine instructions — the execution of machine instructions not in the order in which they appear in the machine code (as was the case with in-order execution (English: in-order execution)), but in the order in which they become ready to execute. It is implemented to increase the performance of computing devices.

Among widely known machines, it was first implemented to a significant extent in the CDC 6600 (Control Data) and the IBM System/360 Model 91 (IBM).

Practically all modern CPU models actually execute instructions not in the order they are received. There is a feature called out-of-order execution, designed to reduce processor idle time while waiting for other instructions to complete.

If the processor determines that the next instruction needs data that will take longer to fetch, it can reorder the instructions, starting work on an unrelated instruction while the fetch is taking place. Out-of-order instruction execution is an extremely useful, but far from the only, auxiliary function of the processor.

Out-of-Order Execution

Description and comparison

Classic in-order execution

When executing instructions in order (English: in-order), the following actions take place:

  1. fetching the instruction;
  2. stalling the processor while waiting to load the instruction's operands;
  3. dispatching the instruction to the corresponding execution unit;
  4. executing the instruction in the corresponding unit;
  5. writing the instruction's execution result to a register cell.

Out-of-order execution

When executing instructions out of order (English: out-of-order), the following actions take place:

  1. fetching the instruction;
  2. placing the instruction into queue I (called the instruction queue, instruction buffer, or reservation stations);
  3. waiting until the operands of any instruction in queue I become available;
  4. dispatching the instruction whose operands are available to the corresponding execution unit;
  5. executing the instruction in the corresponding unit;
  6. writing the instruction's execution result to queue II;
  7. retrieving from queue II the results of those instructions ahead of which there are no remaining unexecuted instructions in queue I, and writing the results to the register file; removing such instructions from queue I.

Features and internal operation

Features of out-of-order execution:

  • an instruction whose operands become ready earlier than those of other instructions can be executed earlier than the others;
  • an instruction placed into queue I later can be executed earlier;
  • the idle time caused by waiting for instruction operands to become ready is reduced (compared to a processor executing instructions in order) because it waits for the operands of several instructions to become ready at once;
  • thanks to the use of queue II, results are written to the register file in the order the instructions appear in the machine code (creating the appearance that instructions are executed in order).

The basic idea of out-of-order execution is to be able to avoid processor idle time in cases where the data needed to execute the next instruction is unavailable. As can be seen above, the processor avoids the stalls that arise at step 2 during in-order execution of instructions, when an instruction cannot be executed because its operands are unavailable.

A processor with out-of-order code execution executes those instructions whose operands are ready, regardless of the order in which the instructions appear in the program code. Instructions are executed not in the order they appear in the program code, but in the order in which data becomes available in the processor's registers. Using queue II, the processor writes the results of instruction execution so as to create the appearance of normal, in-order execution.

Efficiency evaluation

Out-of-order execution is more effective the longer the processor's pipeline, and the greater the difference between the speed of memory (RAM or cache) and the speed of the processor. In modern computers, processors work much faster than memory, so while waiting for data to arrive the processor can execute many instructions whose operands are available.

See also

  • Tomasulo's algorithm
  • Parallel computing
  • Computing pipeline
  • Speculative execution

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