Lecture
Dynamic frequency scaling (also known as throttling, CPU throttling) is a power management technique in computer architecture in which the microprocessor's frequency can be automatically adjusted “on the fly” depending on actual needs, in order to save energy and reduce the amount of heat generated by the chip. Dynamic frequency scaling helps conserve battery charge on mobile devices and reduce cooling costs and noise in quiet computing setups, or it can be useful as a safety measure for overheated systems (for example, after a bad overclock).
Dynamic frequency scaling almost always appears together with dynamic voltage scaling, since higher frequencies require higher supply voltages for the digital circuitry to produce correct results. The combined topic is known as dynamic voltage and frequency scaling (DVFS).
The dynamic power (switching power) dissipated by a chip is equal to C·V 2 ·A·f, where C is the capacitance switched per clock cycle, V is the voltage, A is the activity factor , indicating the average number of switching events per clock cycle by the chip's transistors (as a dimensionless quantity), and f is the clock frequency.
Thus, voltage is the primary factor determining power consumption and heat. The voltage required for stable operation is determined by the frequency at which the circuit is clocked, and it can be reduced if the frequency is also reduced. However, dynamic power alone does not account for the chip's total power, since there is also static power, which is primarily due to various leakage currents. Because of static power consumption and asymptotic execution time, software power consumption has been shown to exhibit convex energy behavior, i.e. there exists an optimal CPU frequency at which power consumption is minimized. Leakage current becomes more and more significant as transistor sizes shrink and threshold voltage levels decrease. A decade ago, dynamic power accounted for roughly two-thirds of a chip's total power. Power losses due to leakage currents in modern CPUs and SoCs tend to dominate total power consumption. In an effort to control leakage power, high-k metal gates and power gating have been common techniques.
Dynamic voltage scaling is another power-saving technique that is often used together with frequency scaling, since the frequency at which a chip can operate is linked to its operating voltage.
The efficiency of some electrical components, such as voltage regulators, decreases as temperature rises, so power consumption can increase with temperature. Since increased power consumption can raise temperature, increasing voltage or frequency can raise the system's power requirements even more than the CMOS formula indicates, and vice versa.
ACPI 1.0 (1996) defines a way for the CPU to enter the “C” idle state, but does not define a frequency scaling system.
ACPI 2.0 (2000) introduces the system of P-states (performance states), which the processor can use to convey its possible frequency-power settings to the OS. The operating system then sets the speed as needed, switching between these states. Regulation technologies such as SpeedStep, PowerNow!/Cool'n'Quiet, and PowerSaver work through P-states. There is a limit of 16 states maximum.
ACPI 5.0 (2011) introduces Collaborative Processor Performance Control (CPPC), giving the OS hundreds of performance levels to choose from in the form of a “performance level”, abstracted away from frequency. This abstraction gives the processor some freedom to tune its operation in ways other than frequency.
A number of modern processors can perform frequency scaling autonomously, using a range of performance levels and an OS “efficiency/performance” hint.
Dynamic frequency scaling reduces the number of instructions the processor can issue in a given time span, thereby reducing performance. It is therefore usually used when the workload is not CPU-bound.
Dynamic frequency scaling by itself is rarely useful as a way to save switching power. Saving as much energy as possible also requires dynamic voltage scaling, because of the V 2 component and the fact that modern CPUs are heavily optimized for low-power idle states. In most cases, at constant voltage it is more efficient to run for a short time at peak speed and then remain in a deep idle state for a longer time (the so-called “race to idle” or computational sprint), than to run at a reduced clock frequency for a long time and remain in a light idle state only briefly. However, lowering the voltage along with the clock frequency can change these trade-offs.
A similar but opposite technology is overclocking, in which processor performance is increased by raising its (dynamic) frequency beyond the manufacturer's specifications.
One of the main differences between them is that in modern PC systems overclocking is mainly performed via the Front Side Bus (mainly because the multiplier is usually locked), whereas dynamic frequency scaling is performed using the multiplier. Moreover, overclocking is often static, while dynamic frequency scaling is always dynamic. Software can often incorporate overclocked frequencies into the frequency scaling algorithm if the risks of chip degradation are acceptable.
Intel's SpeedStep CPU performance regulation technology is used in mobile and desktop processor lines.
AMD uses two different processor regulation technologies. AMD's Cool'n'Quiet technology is used in the desktop and server processor lines. The purpose of Cool'n'Quiet is not to save battery charge, since it is not used in AMD's mobile processor line, but rather to generate less heat, which in turn allows the system fan to spin at lower speeds, resulting in cooler and quieter operation, hence the name of the technology. AMD's PowerNow! processor regulation technology is used in the mobile processor line, although some supporting processors, such as the AMD K6-2+, can also be found in desktop computers.
AMD PowerTune and AMD ZeroCore Power are dynamic frequency scaling technologies for graphics processors.
VIA Technologies processors use LongHaul (PowerSaver) technology, while the Transmeta version was called LongRun.
The 36-core AsAP 1 chip is one of the first multi-core processor chips to support fully unconstrained clock frequency operation (requiring only that frequencies stay below the maximum allowed), including arbitrary frequency changes, starts, and stops. The 167-core AsAP 2 chip is the first multi-core processor chip that allows individual processors to make fully unconstrained changes to their own clock frequencies.
According to the ACPI specification, the working state C0 of a modern CPU can be divided into so-called “P” states (performance states), which allow the clock frequency to be reduced, and “T” states (throttling states), which further reduce CPU performance (but not the actual clock frequency) by inserting STPCLK (stop clock) signals and thus skipping duty cycles.
Various ARM-based systems provide central and graphics processor performance regulation.
Power-saving technologies:
Performance-boosting technologies:
Processor power dissipation
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