ASIC (Application-Specific Integrated Circuit): What It Is and How It Is Designed

ASIC (abbreviated from application-specific integrated circuit, “an integrated circuit for a specific application”) is an integrated circuit specialized for solving a particular task. Unlike ordinary general-purpose integrated circuits, application-specific integrated circuits are used in a particular device and perform strictly limited functions specific to that device; as a result, these functions are carried out more efficiently and, ultimately, more cheaply. An example of an ASIC is a chip designed exclusively to control the radio channel of a mobile phone, or chips for hardware encoding/decoding of audio and video signals (signal processors).

An ASIC chip has a narrow range of application, determined by a rigidly predefined set of its functions.

Modern ASICs often contain a 32-bit or even 64-bit processor, sometimes with several cores, memory blocks (both ROM and RAM), and other large blocks. Such ASICs are often called a system on a chip.

When developing digital ASICs, hardware description languages (HDL) such as Verilog and VHDL are used to describe their functionality.

Early ASICs used gate array technology. By 1967, Ferranti and Interdesign had begun producing the first bipolar gate arrays. In 1967, Fairchild Semiconductor introduced the Micromatrix family, which included bipolar diode-transistor logic (DTL) and transistor-transistor logic (TTL) arrays.

Complementary metal-oxide-semiconductor (CMOS) technology opened the way to widespread commercialization of logic gate arrays. The first CMOS logic gate arrays were developed by Robert Lipp in 1974 for International Microcircuits, Inc. (IMI).

Standard-cell technology based on metal-oxide-semiconductor (MOS) devices was introduced by Fairchild and Motorola under the trade names Micromosaic and Polycell in the 1970s. This technology was later successfully commercialized by VLSI Technology (founded in 1979) and LSI Logic (1981).

A successful commercial application of gate-array-based circuits was found in the inexpensive 8-bit personal computers ZX81 and ZX Spectrum, introduced in 1981 and 1982. Sinclair Research (United Kingdom) used them, in essence, as a low-cost input/output solution intended for handling the computer’s graphics.

Customization was carried out by changing the metal interconnect mask. Gate arrays had a complexity of up to several thousand gates; this is now referred to as medium-scale integration. Later versions became more universal, with various base dies customizable at both the metal and polysilicon layers. Some base dies also included random-access memory (RAM) elements.

In the mid-1980s, a designer would choose an ASIC manufacturer and implement their design using the design tools available from that manufacturer. Although third-party design tools were available, there was no effective link between these tools and the actual characteristics of the semiconductor process of various ASIC manufacturers. Most designers used fab-specific tools to complete the implementation of their designs. The solution to this problem, which also made it possible to obtain devices with much higher density, was the introduction of standard cells. Each ASIC manufacturer could create functional blocks with known electrical characteristics, such as propagation delay, capacitance, and inductance, which could also be represented in third-party tools. Standard-cell design is the use of these functional blocks to achieve very high gate density and good electrical characteristics. Standard-cell design occupies an intermediate position between gate-array design and semi-custom design on one hand, and full-custom design on the other, in terms of non-recurring engineering costs and recurring component costs, as well as performance and development speed (including time to market).

By the end of the 1990s, logic synthesis tools became available. Such tools could compile HDL descriptions into a gate-level netlist. The design of integrated circuits (ICs) based on standard cells is carried out in the following conceptual stages, called the electronic design flow, although in practice these stages overlap significantly:

1. Requirements development: The team of design engineers begins work with an informal understanding of the functions required for the new ASIC, usually obtained through requirements analysis.
2. Register-transfer level (RTL) design: The design team creates a description of the ASIC to achieve these goals, using a hardware description language. This process is similar to writing a computer program in a high-level language.
3. Functional verification: Fitness for the intended purpose is checked through functional verification. This may include methods such as logic simulation using testbenches, formal verification, emulation, or building and evaluating an equivalent pure software model, as in Simics. Each verification method has its own advantages and disadvantages, and ASIC verification most often uses several methods at once. Unlike most FPGAs, an ASIC cannot be reprogrammed after fabrication, so ASIC designs that are not fully correct are far more costly, which increases the need for complete test coverage.
4. Logic synthesis: Logic synthesis converts the RTL design into a large set of low-level constructs called standard cells. These constructs are taken from a standard-cell library consisting of pre-characterized sets of logic gates that perform specific functions. Standard cells are generally specific to the intended ASIC manufacturer. The resulting set of standard cells and the required electrical connections between them are called a gate-level netlist.
5. Placement: The gate-level circuit is then processed by a placement tool, which places the standard cells within the area of the integrated-circuit die that represents the final ASIC. The placement tool attempts to find an optimized arrangement of the standard cells subject to various specified constraints.
6. Routing: An electronic routing tool takes the physical placement of the standard cells and uses the netlist to create the electrical connections between them. Because the search space is large, this process yields a “good enough” rather than a “globally optimal” solution. The result is a file that can be used to produce a set of masks, enabling a semiconductor manufacturing facility, usually called a “fab” or “foundry,” to manufacture physical integrated circuits. Placement and routing are closely interrelated and are jointly referred to in electronic design as place and route. Although logic synthesis, placement, and routing are supported by electronic design automation tools, these stages require considerable guidance and iteration from the designer. Designers set constraints derived from requirements development and RTL design, including timing requirements, placement floorplans, power budgets, and area constraints. Typically, several tool iterations are required to meet performance, power, and area targets, often requiring manual optimization and refinement, which significantly increases the design cycle time.
7. Design closure: Based on the final circuit layout, parasitic resistances and capacitances are calculated. For a digital circuit, this data is then converted into delay information, which can be used to estimate circuit performance, usually by means of static timing analysis. This and other final checks, such as design-rule checking and power analysis, collectively referred to as design closure, are intended to ensure that the device operates correctly under all extreme process, voltage, and temperature conditions. After this testing is completed, the mask information is passed on for chip fabrication.

These stages, carried out with a level of skill typical of the industry, almost always result in a final device that correctly implements the original design, unless defects later arise during physical fabrication.

The design stages, also called the design flow, are likewise common to standard product design. The essential difference is that standard-cell design uses the manufacturer’s cell libraries, which have already been used in perhaps hundreds of other implementations, and therefore carry much less risk than a fully custom design. Standard cells provide cost-effective element placement density and also make it possible to efficiently integrate IP cores and static random-access memory (SRAM), unlike gate arrays.