Harvard architecture is a computer architecture, the distinguishing features of which are:
1. The instruction repository and data repository are different physical devices.
2. The instruction channel and the data channel are also physically separated.

The architecture was developed by Howard Aiken in the late 1930s at Harvard University.

Story

In the 1930s, the US government commissioned Harvard and Princeton universities to develop a computer architecture for naval artillery. And at the end of the 1930s, an architecture was developed by Howard Aiken at Harvard University, named after this university. However, the design of Princeton University (better known as von Neumann architecture, named after the developer who first provided the architecture report) won, as it was easier to implement. Harvard architecture was used by the Soviet scientist A. I. Kitov at the EC-1 of the USSR Ministry of Defense ^[1] .

Classic Harvard Architecture

Typical operations (addition and multiplication) require several actions from any computing device:

1. sample of two operands,
2. selection of instructions and its implementation,
3. and finally saving the result.

The idea implemented by Aiken was to physically separate the command and data lines. In the first computer Aiken "Mark I" for storage of instructions the punched tape was used, and for work with data - electromechanical registers. This made it possible to simultaneously send and process commands and data, thereby greatly improving the overall speed of the computer.

In the Harvard architecture, the characteristics of memory devices for instructions and data memory do not have to be the same. In particular, word width, clocking, implementation technology, and memory address structure may vary. In some systems, instructions can be stored in read-only memory, while data storage usually requires read-write memory. Some systems require significantly more memory for instructions than memory for data, since data can usually be loaded from external or slower memory. This need increases the bit width (width) of the bus address of the memory of instructions compared to the bus address of the data memory.

Difference from von Neumann architecture

In the pure von Neumann architecture, the processor can simultaneously read the instruction, or read / write a unit of data from / in memory. Both cannot occur at the same time, since instructions and data use the same stream ( bus ).

In a computer using the Harvard architecture, the processor can read instructions and access the data memory at the same time, without using cache memory. Thus, a computer with a Harvard architecture, with a certain complexity of the scheme, is faster than a computer with a von Neumann architecture, since the instructions and data buses are located on different channels that are not physically interconnected.

On the basis of the physical separation of command and data buses, the width of these buses (and, therefore, address spaces) can have different values ​​and cannot physically intersect with each other.

Modified Harvard Architecture

The corresponding scheme of implementing access to memory has one obvious disadvantage - high cost. When separating the transmission channels of commands and data on the processor chip, the latter should have almost twice as many pins, since the address bus and the data bus constitute the main part of the microprocessor pins. The way to solve this problem was the idea to use a common data bus and address bus for all external data, and inside the processor to use the data bus, command bus and two address buses. This concept was called the modified Harvard architecture .

This approach is used in modern signal processors. Farther along the path of reducing the cost went when creating single-chip computers - microcontrollers. In them one bus of commands and data is applied inside the crystal.

Separation of tires in a modified Harvard structure is carried out using separate control signals: reading, writing or selecting a memory area.

Extended Harvard Architecture

Often it is required to choose three components: two operands and instruction (in digital signal processing algorithms this is the most common task in FFT of iKI, IIR filters). For this there is a cache memory. The instruction can be stored in it - therefore, both buses remain free and it is possible to transfer two operands simultaneously. Using cache memory along with split tires is called the “Super Harvard Architecture” (“SHARC”) - an extended Harvard architecture.

An example of this is the Analog Devices processors: ADSP-21xx - modified Harvard architecture, ADSP-21xxx (SHARC) - enhanced Harvard architecture.

Hybrid versions with von Neumann architecture

There are hybrid architectures that combine the advantages of both Harvard and von Neumann architectures. Modern CISC-processors have a separate cache memory of the 1st level for instructions and data, which allows them to simultaneously receive both *** and data for its execution in one working cycle. That is, the processor core, formally, is Harvard, but programmatically it is von Neumann, which simplifies the writing of programs. Usually in these processors one bus is used both for sending commands and for transmitting data, which simplifies the system design. Modern variants of such processors can sometimes contain several controllers of several different types of buses for working with different types of memory - for example, DDR RAM and Flash. Nevertheless, in this case, buses are usually used for sending commands and for transmitting data without separation, which makes these processors even closer to the von Neumann architecture while maintaining the advantages of Harvard architecture.

Using

The first computer in which the idea of ​​the Harvard architecture was used was Mark I. Harvard architecture is used in PLC and microcontrollers, such as Microchip PIC, Atmel AVR, Intel 4004, Intel 8051, as well as in the first-level cache memory of x86 microprocessors, divisible into two equal or different in volume blocks for data and commands.