Content - computer circuit design and computer architecture

Subject1. Forms of information. Basic concepts .

Topic 2. The logical basis of building elements.

2.1. Basic concepts, definitions and laws of Boolean algebra .

2.2. The simplest models of logical elements and the system of their parameters .

2.3. Types of output stages of digital elements .

2.4. Systems (series) of logic elements and their main characteristics .

2.5 Test questions .

Theme 3. The design of combinational nodes.

3.1 General Information .

3.2. Encoders, decoders and code converters: purpose, types, operation, principles of construction .

3.3. Synthesis of COP based on decoders .

3.4. Multiplexers and demultiplexers .

3.5. Tire shapers .

3.6 Synthesis of CS based on multiplexers .

3.7. Comparators .

3.8 Adders .

3.9. Arithmetic logic units

3.10. Matrix multipliers .

3.11 Statement and methods for solving problems of combinational node synthesis .

3.12 Criteria for assessing the quality of the technical implementation of the COP .

3.13 Test questions ..

Theme 4. Digital circuit design.

4.1 Sequential digital circuits

4.2. Trigger Circuit Design

4.3. Asynchronous triggers .

4.4. Synchronous Triggers

4.5 Methods for constructing triggers of one type based on triggers of another type

4.6 Registers and Register Files

4.7 Counters

4.8 Tact Dispensers

4.9 Test questions ..

Topic 5. Digital nodes circuit design

5.1 Digital machines and their varieties .

5.2 Abstract and structural automata

5.3. Ways of describing and setting automata

5.4. Relationship between Moore and Mile models

5.5. Minimizing the number of internal states of fully defined automata

5.6. The principle of firmware management. Concepts of operational and control machines

5.7. Graph - schemes of algorithms (GSA) and their varieties. Ways to set up GAW, requirements for them

5.8. Abstract synthesis of Mile and Moore firmware control automata .

5.9. Structural synthesis of Mile and Moore firmware control automata

5.10. Moore Machine Synthesis Based on Shift Register

5.11. test questions

Topic 6. Integrated element systems. Programmable logic devices

6.1 Basic physical principles of programming PLA and FPGA

6.2 Simple and complex PLU

6.3. test questions

Lecture 7. Programmable logic integrated circuits

7.1 Fine, Medium and Large Modular Architectures

7.2 Logical blocks on multiplexers and correspondence tables .

7.3 Compliance tables, distributed RAM, shift registers ..

7.4 Configurable logical blocks, blocks of logical symbols, sections .

7.5 Sections and logical cells .

7.6 Configurable logical blocks CLB and blocks of logical arrays LAB

7.7. Test questions .

Lecture 8 .

8.1 Additional built-in functions .

8.2 Synchronization tree and synchronization managers .

8.3. Systems with tunable architecture .

8.4. User programmable array of nodes .

8.5. Test questions ..

Lecture 9. Operational amplifiers .

9.1. The perfect opamp .

9.2. The basic scheme of the inclusion of the operational amplifier .

9.3 Functional devices on operational amplifiers .

9.4 Active electrical filters at the OS .

9.5 Schemes of nonlinear transformation at the OS .

9.6 Signal Generators at the Shelter

9.7. Test questions ..

Lecture 10 . Circuitry analog nodes.

10.1. Isolation amplifiers .

10.2. Analog Comparators ..

10.3. Sources of reference voltage .

10.4. Analog Switches ..

10.5. Optorele .

10.6. Sample storage devices .

10.7. Digital to analog converters .

10.8. Analog-to-digital converters .

10.9. Test questions ..

Topic 11 Circuitry service elements.

11.1 Interfacing of digital microcircuits manufactured using different technologies and interfacing with interfaces .

11.2 Controlling the inputs of TTL and CMOS ..

11.3 Discrete control of the load from the elements of TTL and CMOS ..

11.4 Transmit digital signals over short distances .

11.5 Test questions ..

Subject 12. Power sources. Circuit design combinatorial nodes.

12.1. Circuit design linear voltage regulators .

12.2 Pulse voltage regulators .

12.3 Inverter circuits ..

12.4 Test questions ..

Topic 13. Digital computers ..

13.1. Principles of digital computers .

13.2. The concept of a software system (mathematical) software .

13.3. Large general-purpose computers .

13.4. Small computers .

13.5. Test questions .

Theme 14. Memory devices.

14.1 Computer memory structure ...

14.2 Methods of memory organization .

14.3. Target memory structures .

14.4 Permanent memory (ROM, PROM) .

14.5. Flash memory

14.6. Test questions ..

Topic 15. Processors

15.1 Operational devices (ALU) .

15.2 Control devices .

15.3. Test questions ..

Theme 16. Universal microprocessors CPU architecture KR580VM80

16.1. Data registers .

16.2. Arithmetic logic unit .

16.3. Register of signs

16.4. Control block

16.5. Buffers .

16.6. MP from the point of view of the programmer .

16.7. Data formats in KR580VM80 .

16.8. Command formats in KR580VM80 .

16.9. Ways of addressing .

16.10. Test questions .

Lecture 17. The system of commands KR580VM80

17.1. Forwarding single-byte .

17.2. Double Byte Transfers

17.3. Battery Operations

17.4. Operations in RON and memory .

17.5. Management teams .

17.6. test questions

Topic 18. The structure of microprocessor systems. General principles ..

18.1. Microcomputer system interface. Bus cycle ..

18.2. Intermediate interface .

18.3. Principles of the organization of input / output information in the microprocessor system

18.4. Test questions .

Lecture 19. Principles of organization of program interruption systems ..

19.1. Interrupt System Characteristics

19.2. Possible interrupt system structures

19.3. Organization of the transition to the interrupting program

19.4. test questions

Lecture 20. Principles of organizing direct memory access systems .

20.1. Ways to organize access to the system backbone .

20.2. Possible structures of the PDP systems ..

20.3. The organization of the exchange in the PDP mode ..

20.4. Microprocessor system based on MP KR580VM80A ..

20.5. Test questions ..

Topic 120. MP support schemes on motherboards.

21.1. The evolution of the IBM PC bus architecture .

21.2. Modern schemes of support for MP on motherboards .

21.3. Test questions ..

Topic 21. Some issues of the development of computer architecture ...

22.1. Tags and handles. Self-detecting data .

22.2. Methods for optimizing the exchange of processor-memory .

22.3. Dynamic memory allocation. Virtual memory

22.4. Test questions ..

Lecture 23. Memory protection .

23.1. Protection of individual memory cells .

23.2. The method of boundary registers .

23.3. Key protection method ..

23.4. Algorithms for managing multi-level memory ..

23.5. Test questions ..

Topic 24. RISK - processors ..

24.1. General characteristics of RISK - processors .

24.2. ARM architecture .

24.3. Test questions ..

Topic 25. Supercomputers. Parallel computing systems ..

25.1. Shifts priorities in high performance computing .

25.2. Applications for multi-core processors and multiprocessor computing systems

25.3. Classification of computer systems architectures according to the degree of data processing parallelism

25.4. SMP, MPP and NUMA architectures ..

25.5. The organization of coherence multi-level hierarchical memory .

25.6. PVP architecture .

25.7. Test questions ..

Lecture 26. Cluster architecture .

26.1. Communication architecture in cluster systems .

26.2. Switches for multiprocessor computing systems.

26.3. Test questions ..

Lecture 27. High-performance multi-core processors for embedded applications

27.1. Tilera Tile-64 / 64Pro processors .

27.2. 96-GFLOPS CSX700 processor from ClearSpeed ​​Technology .

27.3. 167-core computing platform - AsAP-II

27.4. Cell Multiprocessor

27.5. An alternative technology for building multi-core systems on a chip - ATAC .

27.6. Test questions ..

Bibliography..