Lecture
In the design of pipelined computer processors, a pipeline stall is a delay in the execution of an instruction to eliminate a hazard .
In a standard five-stage pipeline, at the decode stage the control unit determines whether the decoded instruction reads data from a register into which an instruction is currently being executed. If this condition holds, the control unit stalls execution of the instruction for one clock cycle. It also stalls the instruction at the fetch stage, to prevent the instruction at that stage from being overwritten by the next instruction in the program. [ 2 ]
In the von Neumann architecture , which uses a program counter (PC) register to determine the current instruction being fetched in the pipeline, in order to prevent the fetching of new instructions while the instruction at the decode stage is stalled, the value in the PC register and the instruction at the fetch stage are held, to prevent changes. The values are held until the instruction causing the conflict has passed the execute stage. [ 3 ] Such an event is often called a “bubble” , by analogy with an air bubble in a pipe of liquid.
In some architectures, the execute stage of the pipeline must constantly perform some action on every cycle. In this case a “bubble” is implemented by feeding NOP instructions (“no operation”) into the execute stage until the “bubble” is flushed out.
Below are two executions of the same four instructions in a four-stage pipeline, but for some reason a delay in fetching the purple instruction in the second cycle results in the formation of a “bubble”, delaying the execution of all subsequent instructions.
The example below shows the insertion of a “bubble” into the classic RISC pipeline with five stages (IF = instruction fetch, ID = instruction decode, EX = execute, MEM = memory access, WB = write-back to register). In this example, the data available after the MEM stage (4th stage) of the first instruction is needed as input data for the EX stage (3rd stage) of the second instruction. Without the “bubble”, the EX stage (3rd stage) has access only to the output data of the previous EX stage. Thus, inserting the “bubble” eliminates the dependency on time without the need to propagate data backward in time (which is impossible).
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